Multi-Level Fixed-Outline Floorplanning Using Convex Optimization

In this paper, we present a novel multi-level fixed-outline convex-optimization floorplanning framework with different objectives on each level of global optimization of wirelength and chip area satisfactions. We solved the framework with a multi-Pass SA-based method for accurate floorplan result generation and significant reduction of the floorplanner running time. The framework started with a clustering method try to classify the modules as a best proposed initialization of the planning for connection-length minimizing. Next, an attractorrepeller model provides the relative positions of the floorplan blocks for wire-length minimizing.  Finally, overlap-free and min deadspace floorplans are achieved in a fixed-outline with any specified percentage of whites-pace for overlapped-length minimizing. The experimental results on the standard benchmarks GSRC and MCNC demonstrate none-overlap floorplans to minimize the wirelength, deadspace and area with significant improvements of run time under complete area utilization as the number of blocks increases.