Automatic Analog IC Layout with CNN-Based Placement Using SqueezeNet and Multi-Objective Routing via DE and NSGA-III

Abstract: The layout design of analog integrated circuits (ICs) is a challenging and time-consuming task, requiring manual effort to extract geometric constraints such as symmetry and proximity. This paper presents a novel approach for automatic layout generation, combining the power of convolutional neural networks (CNNs) with transfer learning, specifically using the pre-trained SqueezeNet model to extract these constraints from schematic images. By applying fine-tuning, the CNN model can effectively identify and extract the necessary geometric relationships, eliminating the need for manual extraction. For the routing process, a multi-objective optimization strategy is employed using the non-dominated sorting genetic algorithm III (NSGA-III), where wire length, via count, and arch segments are minimized. To address the challenge of generating an effective initial population for NSGA-III, we introduce the differential evolution (DE) algorithm as a method for generating high-quality initial solutions, enhancing the convergence speed and solution quality. The proposed methodology is applied to the layout design of a two-stage operational amplifier (op-amp), with simulations conducted using MATLAB and validated in Cadence software on a 0.18μm CMOS process at a 1.8 V supply voltage. The results show that the proposed method signif-icantly outperforms existing techniques in terms of layout efficiency, performance, and automation in the design process.