The CSI Journal on Computer Science and Engineering

Binary Signed-Digit (BSD) Number Representation Efficient Modular Binary Signed-Digit Multiplier for the moduli set {(2^n) -1, 2^n, (2^n) +1} [Volume 9, Issue 2, 2011]

Carry Free Addition Efficient Modular Binary Signed-Digit Multiplier for the moduli set {(2^n) -1, 2^n, (2^n) +1} [Volume 9, Issue 2, 2011]
Cellular Network Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]
Channel Assignment Scheme Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]
Color Moments GPU Implementation of Edge Histogram Descriptor and Color Moments Fused Features for Efficient Image Retrieval [Volume 9, Issue 2, 2011]
Content Based Image Retrieval GPU Implementation of Edge Histogram Descriptor and Color Moments Fused Features for Efficient Image Retrieval [Volume 9, Issue 2, 2011]

Digital Computer Arithmetic Efficient Modular Binary Signed-Digit Multiplier for the moduli set {(2^n) -1, 2^n, (2^n) +1} [Volume 9, Issue 2, 2011]
Directed Retry Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]
DVFS (Dynamic Voltage Frequency Scaling) A Predictive Task Migration Algorithm with Adaptive Migration Threshold for Dynamic Thermal Management of Multi-Core Processors [Volume 9, Issue 2, 2011]
Dynamic Thermal Management A Predictive Task Migration Algorithm with Adaptive Migration Threshold for Dynamic Thermal Management of Multi-Core Processors [Volume 9, Issue 2, 2011]

Edge Histogram Descriptor GPU Implementation of Edge Histogram Descriptor and Color Moments Fused Features for Efficient Image Retrieval [Volume 9, Issue 2, 2011]

Field Programmable Gate Array (FPGA) High Throughput Multi-Pipeline Packet Classifier on FPGA [Volume 9, Issue 2, 2011]

GPU GPU Implementation of Edge Histogram Descriptor and Color Moments Fused Features for Efficient Image Retrieval [Volume 9, Issue 2, 2011]
Guard-Channel Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]

Handoff Calls Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]

Migration Threshold A Predictive Task Migration Algorithm with Adaptive Migration Threshold for Dynamic Thermal Management of Multi-Core Processors [Volume 9, Issue 2, 2011]
Modular Multiplier Efficient Modular Binary Signed-Digit Multiplier for the moduli set {(2^n) -1, 2^n, (2^n) +1} [Volume 9, Issue 2, 2011]
Multi-Core Processors A Predictive Task Migration Algorithm with Adaptive Migration Threshold for Dynamic Thermal Management of Multi-Core Processors [Volume 9, Issue 2, 2011]
Multi-Layer Architecture Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]

Parallel computing GPU Implementation of Edge Histogram Descriptor and Color Moments Fused Features for Efficient Image Retrieval [Volume 9, Issue 2, 2011]
Pipeline-Based Decision Tree High Throughput Multi-Pipeline Packet Classifier on FPGA [Volume 9, Issue 2, 2011]
Placement RF Resource Planning in Application Specific Integrated Circuits to Improve Timing Closure [Volume 9, Issue 2, 2011]

Residue Number System (RNS) Efficient Modular Binary Signed-Digit Multiplier for the moduli set {(2^n) -1, 2^n, (2^n) +1} [Volume 9, Issue 2, 2011]
RF Interconnects RF Resource Planning in Application Specific Integrated Circuits to Improve Timing Closure [Volume 9, Issue 2, 2011]
Rule Set High Throughput Multi-Pipeline Packet Classifier on FPGA [Volume 9, Issue 2, 2011]

Sub Rating Performance Analysis in Double Layer Cellular Network with New Call Bounding Scheme and Directed Retry [Volume 9, Issue 2, 2011]

Task Migration A Predictive Task Migration Algorithm with Adaptive Migration Threshold for Dynamic Thermal Management of Multi-Core Processors [Volume 9, Issue 2, 2011]