Approximate Carry Save Adders Lead to an Efficient Implementation of Low-latency Two-Dimensional Gaussian Smoothing Filter

Document Type : Original Article

Authors
Hadise Ramezani 1
Majid Mohammadi 2
Amir Sabbagh Molahosseini 1
1 Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran
2 Department of Computer Engineering, Shahid Bahonar University of Kerman, Kerman, Iran
10.22034/jcse.2023.182036
Abstract
One of the popular filters in image processing is the two-dimensional Gaussian smoothing filter (2D-GSF). An efficient implementation and design of 2D-GSF in real-time processing are significantly important since requiring high computing resources. A modern technique capable of reducing the 2D Gaussian filter design's latency and increasing the performance with insignificant computing overhead on field programmable gate arrays (FPGA) is called approximate computing. The present research's objective is presenting a low-latency Gaussian filter architecture on FPGA to be applied in real-time processing. Therefore, approximate and accurate carry-save adders (CSAs) were employed in Gaussian filters based on the adder tree. The implementation and simulation results prove the latency reduction in 3x3 2D-GSF architectures up to 45% and 22% by applying proposed approximate CSAs and accurate CSAs, respectively, compared to the available Gaussian filters with an adder tree structure. Output image quality decreases by an inconsiderable rate of 1.2% in approximate design.
Keywords
2D Gaussian smoothing filter
Approximate computing
FPGA Implementation
Carry save adder
two-dimensional Gaussian smoothing filter (2D-GSF)