Improving testability during the early stages of High-level Synthesis (HLS) has several benefits including reduced test hardwar, overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/observability are considered. Experiments show using this register allocation method results in significant improvement in ATPG time and fault coverage.
Safari,S. , Jahangir,A. and Esmaeilzadeh,H. (2003). A New Register Allocation Method For Testability Improvement. (e215817). The CSI Journal on Computer Science and Engineering, 1(3), e215817
MLA
Safari,S. , , Jahangir,A. , and Esmaeilzadeh,H. . "A New Register Allocation Method For Testability Improvement" .e215817 , The CSI Journal on Computer Science and Engineering, 1, 3, 2003, e215817.
HARVARD
Safari S., Jahangir A., Esmaeilzadeh H. (2003). 'A New Register Allocation Method For Testability Improvement', The CSI Journal on Computer Science and Engineering, 1(3), e215817.
CHICAGO
S. Safari, A. Jahangir and H. Esmaeilzadeh, "A New Register Allocation Method For Testability Improvement," The CSI Journal on Computer Science and Engineering, 1 3 (2003): e215817,
VANCOUVER
Safari S., Jahangir A., Esmaeilzadeh H. A New Register Allocation Method For Testability Improvement. CSIonJCSE, 2003; 1(3): e215817.
The CSI Journal on Computer Science and Engineering