In this paper, a low-power energy-efficient hierarchical SRAM design capable of working in near-threshold region is proposed. The proposed method enhances the noise margin using an extra circuitry, while restricting the hardware redundancy by sharing the additional circuitry between each two SRAM cells in a hierarchical style. The results of simulating the FinFET-based SRAM cells using Synopsys HSPICE at 10nm technology node indicate that the proposed design reduces, on average, the power-delay product, read and write delays by 14.34%, 2.37% and 8.54%, respectively, and significantly improves the static noise margins even in the presence of major process variations.
Maabi,S. , Sayyah Ensan,S. , Hossein Moaiyeri,M. and Hessabi,S. (2016). A Low-Power Hierarchical FinFET-Based SRAM. (e215882). The CSI Journal on Computer Science and Engineering, 13(2), e215882
MLA
Maabi,S. , , Sayyah Ensan,S. , , Hossein Moaiyeri,M. , and Hessabi,S. . "A Low-Power Hierarchical FinFET-Based SRAM" .e215882 , The CSI Journal on Computer Science and Engineering, 13, 2, 2016, e215882.
HARVARD
Maabi S., Sayyah Ensan S., Hossein Moaiyeri M., Hessabi S. (2016). 'A Low-Power Hierarchical FinFET-Based SRAM', The CSI Journal on Computer Science and Engineering, 13(2), e215882.
CHICAGO
S. Maabi, S. Sayyah Ensan, M. Hossein Moaiyeri and S. Hessabi, "A Low-Power Hierarchical FinFET-Based SRAM," The CSI Journal on Computer Science and Engineering, 13 2 (2016): e215882,
VANCOUVER
Maabi S., Sayyah Ensan S., Hossein Moaiyeri M., Hessabi S. A Low-Power Hierarchical FinFET-Based SRAM. CSIonJCSE, 2016; 13(2): e215882.
The CSI Journal on Computer Science and Engineering