FinFET Based Level Converter for Multi-VDD System Design

Low-power design is the most demanding for nanoscale integrated circuits design. Aggressive low-power design to maximize the battery life is a significant challenge especially in battery-powered digital VLSI systems. Multi-VDD design is an effective approach for low power design. However, in these Multi-VDD systems, the existence of voltage Level Converters (LCs) between these different voltage islands is necessary. Deigning low power and low cost LC is a significant challenge to reduce the LCs overhead in multi-VDD systems. In this paper a Single-Supply Level Concreter (SSLC) based on independent-gate FinFET is proposed. In the proposed technique, the back gate of FinFETs is biased for providing multi-threshold voltage (Vt) design in order to reduce the number of required transistors in converting low-voltage input signals and decrease static power consumption. Simulation analyses utilizing 22nm technology model demonstrate a qualified performance of the proposed low area and low power design compared to the other previously published most efficient designs.