To help overcome limits to the speed and density of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM uses one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor cell using same design rules. Simulation results obtained from HSPICE 2008 in 0.25µm technology show new cell is 27% faster than conventional six-transistor cell. Furthermore, the analytical results are in good agreement with the improvement of speed in new cell.
Azizi Mazreah,A , Taghi Manzuri,M and Noorallahi Romani,M . (2008). A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications. (e216013). The CSI Journal on Computer Science and Engineering, 6(1), e216013
MLA
Azizi Mazreah,A , , Taghi Manzuri,M , and Noorallahi Romani,M . "A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications" .e216013 , The CSI Journal on Computer Science and Engineering, 6, 1, 2008, e216013.
HARVARD
Azizi Mazreah A, Taghi Manzuri M, Noorallahi Romani M. (2008). 'A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications', The CSI Journal on Computer Science and Engineering, 6(1), e216013.
CHICAGO
A Azizi Mazreah, M Taghi Manzuri and M Noorallahi Romani, "A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications," The CSI Journal on Computer Science and Engineering, 6 1 (2008): e216013,
VANCOUVER
Azizi Mazreah A, Taghi Manzuri M, Noorallahi Romani M. A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications. CSIonJCSE. 2008;6(1):e216013.
The CSI Journal on Computer Science and Engineering