Novel ternary multipliers improved in size and performance based on carbon nanotube transistor

Document Type : Original Article

Authors
Masoud Mahjoubi 1
Saadat Pourmozafari 2
Kooroush Manochehri 1
1 Department of Computer engineering and IT, Amirkabir University of Technology-Garmsar Campus
2 Prof at Department of computer engineering and IT, Amirkabir University of Technology-Garmsar Campus
10.22034/jcse.2025.218592
Abstract
The multiplier is the basic computational operation in ALUs and impacts on their performance and chip size. Carbon nanotube field effect transistors (CNFETs) are used in many designs to enhance their performance, area, and power dissipation. Moreover, using CNFET results multi-value logic (MVL) -i.e., ternary logic. Using ternary logic in circuits results in chip size reduction due to its less connection than binary logic. In this paper, two novel ternary multipliers based on CNFET are proposed. The number of transistors is reduced about 15% in the first proposed design compared with the best-reported result. The PDP of the second proposed circuit is reduced about 57% in comparison with the best design. Stanford's 32-nanometer model, the HSPICE software, and same input signals are used to investigate the criteria of simulation of multiplier circuits.
Keywords
Multiplier
CNFET
MVL
Ternary